Roadmap

Where things stand.

Tessera is actively developed. v1.0 is out and fully functional, with a complete 7-pass transpiler pipeline with three hardware backends, a full test suite, and benchmarks. Here's what's shipped, what's coming next, and what we're thinking about further out.

v1.0Shipped

Initial Release

✓TesseraCircuit intermediate representation (IR)
✓7-pass transpiler pipeline (basis translation → layout → routing → optimization)
✓Basis translation pass with per-backend decomposition maps
✓Dense layout pass with greedy qubit assignment by interaction frequency
✓SWAP router for non-adjacent two-qubit gate resolution
✓Remove barriers pass for pre-optimization cleanup
✓Adjacent gate cancellation pass (X·X, H·H, CX·CX, and others)
✓Rotation merging pass with configurable epsilon threshold
✓
IBM backendHeavy-hex topology
Nairobi7q · defaultBrisbane127qSherbrooke127q
✓
IonQ backendAll-to-all connectivity
Aria25q · defaultForte36q
✓
Rigetti backendSquare lattice topology
Ankaa84q · defaultAnkaa-9Q9q
✓Full unit test suite for all passes and backends
✓Integration test suite: logical circuit → fully transpiled output
✓Benchmark suite comparing gate count and depth against Qiskit's transpiler
✓PyPI distribution structure (setup.py, pyproject.toml)
✓Public documentation site (this site)

v1.xPlanned

Optimizations

Performance and quality improvements to the existing pipeline, including smarter optimization passes and reduced gate overhead.

·Commutative gate rewriting: reorder gates that commute to create cancellation opportunities
·Multi-pass optimization loop: repeat cancellation and merging until the circuit stabilizes
·Noise-aware layout: weight qubit assignment by device error rates in addition to connectivity
·SABRE / A* routing: replace the greedy SWAP router with a lookahead-based strategy

v2.xConsidering

Further Out

Ideas we're thinking about but haven't committed to. The Developer Platform in particular is early-stage but worth calling out. It would be a visual circuit debugger showing the circuit state at each pass boundary.

·Custom backend definitions via YAML/JSON config file
·Backend capability introspection API
·Additional IBM device coupling maps (Heron, Condor)
·Developer Platform: visual circuit debugger that shows the circuit state at each pass boundary