Where things stand.

Initial Release

• ✓TesseraCircuit intermediate representation (IR)
• ✓7-pass transpiler pipeline (basis translation → layout → routing → optimization)
• ✓Basis translation pass with per-backend decomposition maps
• ✓Dense layout pass with greedy qubit assignment by interaction frequency
• ✓SWAP router for non-adjacent two-qubit gate resolution
• ✓Remove barriers pass for pre-optimization cleanup
• ✓Adjacent gate cancellation pass (X·X, H·H, CX·CX, and others)
• ✓Rotation merging pass with configurable epsilon threshold
• ✓
  IBM backendHeavy-hex topology

  Nairobi7q · defaultBrisbane127qSherbrooke127q
• ✓
  IonQ backendAll-to-all connectivity

  Aria25q · defaultForte36q
• ✓
  Rigetti backendSquare lattice topology

  Ankaa84q · defaultAnkaa-9Q9q
• ✓Full unit test suite for all passes and backends
• ✓Integration test suite: logical circuit → fully transpiled output
• ✓Benchmark suite comparing gate count and depth against Qiskit's transpiler
• ✓PyPI distribution structure (setup.py, pyproject.toml)
• ✓Public documentation site (this site)

Pluggable Algorithms & Optimization Loop

Layout and routing become registry-pluggable, each with three algorithms out of the box plus a custom-callable escape hatch. Cancel Adjacent and Merge Rotations gain a wrapping optimization loop that can run a fixed number of iterations or iterate until gate count converges. All additive at default settings, so existing v1.0 code keeps working unchanged.

• ✓Pluggable layout algorithm selection: dense (default), SABRE, and trivial
• ✓Pluggable routing algorithm selection: BFS (default), A*, and SABRE
• ✓SABRE layout: forward-backward trial routing for initial mapping discovery (Li, Ding, Xie 2019)
• ✓A* routing: shortest-path search with admissible heuristic, ready for noise-aware weighted edges
• ✓SABRE routing: whole-circuit swap selection with front-layer lookahead
• ✓Multi-pass optimization loop with fixed-iteration and convergence modes
• ✓New transpile() parameters: layout_algorithm, optimization_iterations, max_iterations
• ✓The routing pathfinder argument now accepts a registered algorithm name in addition to the custom callables it accepted before, with full backwards compatibility
• ✓Commutative mode (strict=False) for Cancel Adjacent and Merge Rotations, now documented
• ✓Sparse-layout routing fixes across BFS, A*, and SABRE for partial mappings on real hardware coupling maps

Broader Reach & Developer Tooling

Stretching Tessera beyond its current hardware lineup, smarter qubit placement that accounts for device noise, and tools that make the transpilation process easier to inspect end to end.

• ·Noise-aware layout and routing: weight qubit placement and pathfinding by device error rates, building on the A* hooks added in v1.1
• ·Developer Platform: a visual circuit debugger that shows the circuit state at each pass boundary
• ·Broader hardware backend support: more devices on the existing IBM, IonQ, and Rigetti backends, plus the option to add entirely new platforms beyond them

Further Out

Ideas we're thinking about but haven't committed to yet. A mix of ecosystem reach, deeper pluggability, and tooling that would round out the project once the v1.x work is in place.

• ·Backend capability introspection API: programmatic queries for a backend's basis gates, coupling map, and other metadata
• ·Third-party algorithm plugins: external Python packages can register new layout or routing algorithms without forking Tessera
• ·OpenQASM 3 input and output: read and write circuits in the hardware-agnostic OpenQASM 3 format alongside Qiskit circuits
• ·Mid-circuit measurement and dynamic circuits: first-class IR support for measuring qubits mid-circuit and applying gates conditional on the result
• ·Equivalence verification: an optional debug pass that simulates the input and transpiled circuits and asserts they are unitarily equivalent
• ·Command-line interface for transpiling circuits directly from a shell without writing Python